[sv-bc] logic keyword

logic is a keyword in systemVerilog and it is also a very broadly used
discipline name in Verilog ams. The issue is that logic cannot coexist as
both a logic digital type identifier and a discipline type identifier,
which means that this would cause problems with users trying to use both
systemVerilog and Verilog AMS in the same module.

I think I remember someone (It may have been Kevin) bringing this up a long
time ago and I can't remember what was the desicion made. Can someone let
me know what was the outcome of the discussion.

Francoise
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Received on Thu Mar 18 07:30:46 2004