[sv-bc] cross - not an SV 3.1 keyword - is an SV 3.1a keyword

Hi All -

Another minor typo on Table B-1.

"cross" is listed as a SystemVerilog 3.1 keyword. In fact, it is a
SystemVerilog 3.1a keyword.

Interesting side-note:
SystemVerilog 3.0 - 43 new keywords (reduced to 36 new keywords after SV 3.1)
SystemVerilog 3.1 - 43 new keywords
SystemVerilog 3.1a - 18 new keywords

Using bug-tracking methods, since SV 3.1a saw a dramatic drop in new
keywords, OBVIOUSLY, we are nearing product release (just like diminishing
new bug reports!)

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
Received on Tue Mar 23 18:27:38 2004