RE: [sv-bc] Interface modports vs. logic synthesis

Hi Brad,

this implies that vertical use of interfaces (hierarchical top-down) is limited
as drivers for interface objects may be scattered throughout the different
hierarchies. The designer therefore has to convert the interface into ordinary
signals/objects in the local toplevel and then distribute manually to the lower
levels. This reduces the usability of interfaces significantly for RTL design.

Horizontal use of interfaces (e.g. a bus system connecting units to a bus) will
function fine with the restriction.

- Peter

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Brad
Pierce
Sent: 19. marts 2004 20:02
To: sv-bc@eda.org
Subject: Re: [sv-bc] Interface modports vs. logic synthesis

Peter,

>Question: Should the LRM prescribe that connection bewteen different
>modport-subsets of the same interface is allowed, assuming these subsets
>are compatible?

The following clarification was recently approved as part of LRM-291 --

    If a port connection specifies a modport list name in both
    the module instance and module header declaration, then
    the two modport list names shall be identical.

See http://www.eda.org/sv/Changes_draft6/LRM_Changes_19.html .

-- Brad
Received on Thu Apr 1 05:35:51 2004