[sv-bc] SystemVerilog 3.1A Errata Development

Dear SV members,
        On June 3, we had a face to face meeting with all committees.
The minutes and a set of presentations will be posted on the SV website
soon.
        We will continue Accellera SystemVerilog efforts by starting a
SystemVerilog-3.1A-E where e standards for Errata. It is important for
Accellera and this committee to provide a continual support to Accellera
Standard 3.1A. The mains focus is to help implementers (EDA vendors, and
tool developers) and users (modeling, chip designs, etc) by clarifying
semantics and issue errata document. We will not add or enhance the
language. We believe that SystemVerilog is ready to use right now. So it
is important for the community (implementers and users) to support this
effort by:

1- Issuing Bug reports based on "real experience".
2- Issuing clarification requests.
3- You can also identify enhancements. We will collect them for future
development.

        All four committees will operate as usual. We will address
errata and clarification using Accellera process. We will also issue
errata list plus a full LRM where corrections will be shown with change
bars.

        David Smith has installed a bug tracking system. We will use
this bug tracking system. Every chair and champion will be able to
report and close any bug/clarification based on voting process of each
committee. Accellera Members will have special accounts to be able to
report bugs and clarification (one account per Accellera Member
Company). David will issue a procedure of how to access and use this bug
tracking system. David Smith deserves our thanks for spending weekends
developing this system for Accellera.

        When you report a bug please add Errata as the first word in the
subject. When you report a clarification please add clarify as the first
word in the subject. When your report an enhancement, please do so as
the first word in the subject.

        In the SV meeting we also discussed our relationship with IEEE
1800 (SystemVerilog) and IEEE 1364 (Verilog 2005) groups. It is our
intention to work closely with both groups and synchronize all
activities. Currently IEEE 1800 is in the formation stage. Once the
group starts to function, we will cooperate fully with their wishes and
also with the collective wish of the 1364. Our main goal is to support
Accellera SystemVerilog 3.1A as the main standard for the industry to
develop and use.

Best Regards

Vassilios
Received on Thu Jun 17 22:45:55 2004