Re: [sv-bc] Erratum and proposal in casting BNF

Steve,

The SV-BC passed an erratum
(http://www.eda.org/sv-bc/display_issue.cgi?issue_num=38) that makes the
operand of a cast context determined.

And yes, $signed provides similar functionality, but because it is a
system function, it cannot be used in a constant expression.

Dave

Steven Sharp wrote:

>>I think casting the signedness of a concatenation does make sense. The
>>result of a concatenation is always unsigned, even if its members are
>>signed. If the concatenation is in a compound expression, I may still wish
>>to treat the msb of the resultant concatenation as a sign bit, instead of a
>>significant bit. E.g.:
>>
>> reg signed [31:0] a;
>> reg [15:0] b;
>> reg signed [47:0] c;
>>
>> if ( c < signed'{a,b} ) ...
>>
>>
>
>Note that this can be done in Verilog-2001 by using the $signed() system
>function.
>
>Is the operand of a cast self-determined? I assume so.
>
>Note that C does not support casting just the signedness of a value without
>providing a full type. You cannot use a "signed" cast that will cast an
>unsigned int to a signed int and an unsigned long to a signed long. If you
>try, you will find that (signed) is just shorthand for (signed int).
>
>Steven Sharp
>sharp@cadence.com
>
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625