Re: [sv-bc] Clarify -- Type casting issue]

Yes. It's the same as if the cast was a separate assignment to a
temporary variable. i.e

A = cast_t1'(expr_1) + cast_t2'(expr_2);

should be the same as

cast_t1 temp1;
cast_t2 temp2;

A = (temp1 = expr_1) + (temp2 = expr_2);

which is the same as

temp1 = expr_1;
temp2 = expr_2;
A = temp1+ temp2;

All these assume that there is an implicit cast defined for these types.

Dave

Steven Sharp wrote:

>>This issue reversed that decision. It was too late to make it into the
>>SV3.1a LRM
>>
>>
>
>So an operand of a cast is context-determined, where the context includes
>the type being cast to, but includes nothing outside the cast?
>
>
>Steven Sharp
>sharp@cadence.com
>
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625