Steven Sharp wrote:
>>And yes, $signed provides similar functionality, but because it is a
>>system function, it cannot be used in a constant expression.
>>
>>
>
>This is true in Verilog-2001. However, SystemVerilog is allowing $bits
>to be used in constant expressions. With this precedent, I don't see
>why $signed could not be allowed in constant expressions also.
>
>
Yes, I agree that should be done. But now that SV has a more general
casting mechanism, its seems more natural to use the casting syntax to
change the signing rather than a system function.
>There is also a proposal for 1364-2005 that $signed and other appropriate
>system functions be allowed in constant expressions.
>
>Steven Sharp
>sharp@cadence.com
>
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant and/or Principal Product Engineer http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625Received on Tue Jun 22 22:48:31 2004
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