[sv-bc] Re: System Verilog: 'reg' and 'logic' interchangeable?

Ralph,

(I am coping this to the SV-BC since I am only one opinion)

One of the significant changes in the Verilog-2001 LRM was to update the
terminology of 'Register' to 'Variable', without changing any of their
semantics. The reasoning behind this was because the term 'Register' is
misleading in describing hardware when an object of type 'reg is not
always intended to be turned into a register.

In the Verilog-2001 LRM, reg, integer, time, and real are all classified
as variables, with all the same semantics in terms of where they can be
used and how they are written to. The only significant difference in
their declarations is that 'reg' can be declared with a single packed
dimension. However the PLI, for mostly historical reasons, treats 'reg'
and the other variables as separate categories of objects.

In the Superlog language, the 'logic' type was created as a variable,
just like time, real, and integer. All variables were enhanced in
Superlog by allowing them to be driven by a single continuous
assignment, and to be passed through ports. 'reg' was left untouched,
not because of any backward compatibility problems, but because the
Verilog-2001 behaviour of 'reg' was too engrained everywhere to be
tampered with (People would miss their 'illegal left-hand assignment'
errors). If you only made procedural assignments to 'logic' then it was
semantically equivalent to 'reg'

The SystemVerilog BC committee felt that keeping 'reg' in a category by
itself was not needed. So they added all of the semantic enhancements to
'reg' (i.e. allowing continuous assignments), making it equal to 'logic'
in every way except in name and its PLI access type.

So why not drop 'logic' altogether as it is now a redundant feature?
Because now that all variables can be continuously assigned, the keyword
'reg' has even less meaning than it did in Verilog-2001. Most of the
SystemVerilog trainers that I know have dropped mentioning 'reg' at all
in favour of 'logic'. 'The term 'logic' is also used in SystemC and VHDL
when describing a similar type of object.

Dave

Duncan, Ralph wrote:

>Thanks very much for your reply and for the vector to the PDF material.
>
>I've suggested to SV-CC that we make our treatment of reg/logic for
>DPI purposes explicit in the relevant section. We'll see what happens.
>
>Aside: At first I thought the logic/reg difference was hiding in 5.6
>assignment
>limitations: "In System Verilogm, all variables can now be written..." but
>this says
>in-SV-all-variables, rather than all variables of an SV type.
>
>Being ugly and obvious: If there is no semantic distinction between 'logic'
>and 'reg' why, then, was 'logic' added?
>
>Thanks again for any light you can shed,
>Ralph
>
>
>
>
>
>
>>-----Original Message-----
>>From: Dave Rich [mailto:David.Rich@synopsys.COM]
>>Sent: Monday, July 26, 2004 11:44 PM
>>To: Duncan, Ralph
>>Cc: Warmke, Doug
>>Subject: Re: System Verilog: 'reg' and 'logic' interchangeable?
>>
>>Hi Raplh,
>>
>>As you noted, 'logic' and 'reg' are equivalent types because
>>they are both 4-state bit level variable types as defined by
>>section 5.8.1, rule 5.
>>They are not identical, because they do not have the same
>>built-in name; just like wire and tri are equivalent net
>>types, but have different names.
>>Is there any real difference between the two types? No, just
>>their name is different.
>>
>>For some history, read the first 3 paragraphs of
>>http://boydtechinc.com/lst0tf/archive/att-0044/01-First_some_b
>>ackground.pdf
>>(This is from an 1364-2005 working sub-group on data types,
>>trying to propose data types on nets. This has not been
>>presented to any SystemVerilog committee) Dave
>>
>>
>>Duncan, Ralph wrote:
>>
>>
>>
>>>Mr. Rich,
>>>
>>>Doug Warmke suggested you as our ultimate authority on
>>>
>>>
>>System Verilog
>>
>>
>>>data type matters.
>>>
>>>The following issue arises about the relationship between the data
>>>types 'reg' and 'logic':
>>>
>>> Should one assume that the data types 'reg' and 'logic' are
>>>effectively interchangeable
>>> in the System Verilog language (in LRM 3.1a), given the following:
>>>
>>> a. The only apparent difference is that reg is termed a
>>>"Verilog-2001" type and logic
>>> a "System Verilog" type (LRM 3.3 table 3-1).
>>>
>>> b. Section 3.1 neither distinguishes type 'logic' from 'reg' nor
>>>says they are interchangeable.
>>>
>>> c. Although there seems to be no material difference in
>>>
>>>
>>the two, one
>>
>>
>>>hesitates to treat them as
>>> synonymous, since section 5.8 makes the following proclamation:
>>>
>>> "Note that there is no category for identical types
>>>
>>>
>>defined here
>>
>>
>>>because there is no construct
>>> in the System Verilog language that requires it."
>>>
>>>Q1: Despite 5.8, does any LRM section effectively say reg and logic
>>>can be treated as being identical?
>>>
>>>Q2: Do the type equivalence rules in 5.8.1 suffice for this purpose?
>>>
>>>Q3: Are there any real differences in behavior between the two?
>>>
>>>Thanks very much for any advice you can provide, Ralph Duncan
>>>
>>>Staff Engineer
>>>Mentor Graphics
>>>San Jose, CA
>>>rduncan@model.com
>>>408-487-7414
>>>
>>>
>>>
>>--
>>--
>>David.Rich@Synopsys.com
>>Technical Marketing Consultant and/or
>>Principal Product Engineer
>>http://www.SystemVerilog.org
>>tele: 650-584-4026
>>cell: 510-589-2625
>>
>>
>>
>>
>
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625