Re: [sv-bc] Re: System Verilog: 'reg' and 'logic' interchangeable?

Just a side note on why the term 'variable' was introduced in 1364-2001.
It was also because a term was needed to refer to all the types of
variables whereas the terms 'reg' and 'register' might be interpreted to
mean only the 'reg' type.

Here is an excerpt from a mail by Stu Sutherland on Jan 18, 2000:

" The 1364-1995 LRM used a mixture of terms to describe the reg, integer,
time, real and realtime data types, such as "registers", "variables", and
"register variables". A change was approved to eliminate the confusing
"register" term in the LRM, and consistently refer to these data types as
either "variables" to indicate the entire class, or "reg" to refer to just
that specific data type.

The implementation of the change was not complete, plus, in many places, a
global search and replace used the term "reg" "register", when "variable"
should have been used (to indicate the full class of data types).

Here are the hundred or so places I found that need to be changed..."

Shalom

-- 
Shalom Bresticker                        Shalom.Bresticker @freescale.com
Design & Reuse Methodology                           Tel: +972 9  9522268
Freescale Semiconductor Israel, Ltd.                 Fax: +972 9  9522890
POB 2208, Herzlia 46120, ISRAEL                     Cell: +972 50 5441478
  
[ ]Freescale Internal Use Only      [ ]Freescale Confidential Proprietary