[sv-bc] Question on 19.6.3 An example

Hi,

The example shows how the task Read and the task Write are exported from module
memMod to the interface simple_bus.
The example also shows how the tasks Read and Write are imported from
simple_bus to module cpuMod.

My question is why the tasks Read and Write without task input ports can be
passed with actuals in module cpuMod?

Thanks for the help.

Regards,
Andy
Received on Thu Jul 29 11:36:48 2004