Re: [sv-bc] Partial proposal for issue #091- take #2

Shalom.Bresticker@freescale.com wrote:

>Hi,
>
>As I wrote previously, in Verilog hierarchical references in parameter
>overrides in module instance statements are allowed, whereas they are
>not in parameter declarations and in defparams.
>
>I don't know the reason.
>
>Maybe it is a mistake to allow them in module instance statements
>as well.
>
>

I would encourage the deprecation of this. At least it would be wise to
block it outright for any new construct, like type parameters and xmr
interface instances.
    _Matute
Received on Tue Aug 24 06:50:34 2004