Re: [sv-bc] Partial proposal for issue #091- take #2

>As I wrote previously, in Verilog hierarchical references in parameter
>overrides in module instance statements are allowed, whereas they are
>not in parameter declarations and in defparams.
>
>I don't know the reason.

Probably a matter of the two being implemented independently in Verilog-XL.

>Maybe it is a mistake to allow them in module instance statements
>as well.

It certainly creates an inconsistency where overrides in instantiation
don't follow the normal rules for constant expressions.

Steven Sharp
sharp@cadence.com
Received on Wed Aug 25 17:47:13 2004