Re: [sv-bc] precedence of :/ vs. //

> However, if your tool has a Verilog2001 mode and a SystemVerilog mode,
> the :// in your example would have to be preprocessed as
> : // (2 tokens) for 2001, and as
> :// (1 token) for SystemVerilog.

What do you mean that "://" is one token in SystemVerilog? I don't see any
"://" token in the lrm. (Or has one been added since 3.1a draft 6?)

The problem is that SystemVerilog needs to be backwards compatible (as
much as possible) with standard Verilog. I ran across this "://"
problem in an existing verilog test case.

The "///" problem wasn't an issue for C/C++ since "///" could never occur
in a valid C program (except within a /* ... */ comment).

Paul
Received on Wed Aug 25 07:25:23 2004