Re: [sv-bc] Partial proposal for issue #091- take #2

But is it a problem that hierarchical references are allowed in the module
instance statement parameter overrides?

Shalom

Steven Sharp wrote:

> >As I wrote previously, in Verilog hierarchical references in parameter
> >overrides in module instance statements are allowed, whereas they are
> >not in parameter declarations and in defparams.
> >
> >I don't know the reason.
>
> Probably a matter of the two being implemented independently in Verilog-XL.
>
> >Maybe it is a mistake to allow them in module instance statements
> >as well.
>
> It certainly creates an inconsistency where overrides in instantiation
> don't follow the normal rules for constant expressions.
>
> Steven Sharp
> sharp@cadence.com

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