[sv-bc] Errata: enum initial values won't simulate design initialization

An enum is defined in table 5-1 to have a default initial value of the
first value in the enumeration.

A 4-state enum variable will frequently represent a hardware register,
such as a state register for a state machine. Simulating correct design
initialization requires registers to be initialized to X. Starting a
state register at any other value will give optimistic results, and could
prevent finding power-up problems. These could be very expensive for
users.

Presumably the first enumeration value was chosen to make sure that the
initial value was one of the "legal" values, to try to preserve the
semi-strong typing (this is not actually strong typing, since there are
ways to circumvent it). The easiest solution to this is to remove the
attempt at strong typing for enums. It is not consistent with the rest
of the Verilog language anyway, since very loose type rules are used
everywhere else in the language.

Correct simulation of circuit initialization is more important than the
supposed benefits of strong typing on one type in a language that is
otherwise very loose.

Steven Sharp
sharp@cadence.com
Received on Tue Aug 31 16:37:24 2004