[sv-bc] Errata: variable initializers don't match Verilog-2001

From: Steven Sharp <sharp@cadence.com>
Date: Tue Aug 31 2004 - 16:10:09 PDT

This is well known, but has not been addressed in P1800.

The semantics of variable initializers in SystemVerilog do not match the
semantics defined in Verilog-2001. This is even explicitly acknowledged
in the LRM.

Steven Sharp
sharp@cadence.com
Received on Tue Aug 31 16:10:12 2004

This message: [ Message body ]
Next message: Steven Sharp: "[sv-bc] Errata: enum initial values won't simulate design initialization"
Previous message: Steven Sharp: "[sv-bc] Errata: inconsistent time literal rules"
Next in thread: Shalom Bresticker: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Reply: Shalom Bresticker: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Jay Lawrence: "RE: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Clifford E. Cummings: "RE: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Rich, Dave: "RE: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Reply: Shalom.Bresticker@freescale.com: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Rich, Dave: "RE: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Brad Pierce: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "RE: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "RE: [sv-bc] Errata: variable initializers don't match Verilog-2001"
Maybe reply: Steven Sharp: "Re: [sv-bc] Errata: variable initializers don't match Verilog-2001"

Contemporary messages sorted: [ By Date ] [ By Thread ] [ By Subject ] [ By Author ] [ By messages with attachments ]

This archive was generated by hypermail 2.1.8 : Tue Aug 31 2004 - 16:10:28 PDT