RE: [sv-bc] Errata: variable initializers don't match Verilog-2001

>From: "Mark Hartoog" <Mark.Hartoog@synopsys.com>

>I think the requirement is that all initial values must be assigned
>throughout the design before any user initial blocks starts.

That might be a desirable thing, and it might be reasonable to require
it. But it is definitely *not* desirable to have initial values assigned
before always blocks start.

>By the way, with the addition of 2 state variables, you have this problem
>even without initial values.

Yes, that is a problem when you take a language that was designed to work
properly with 4-state values and throw 2-state values in after the fact.
However, new SystemVerilog code has the option of using always_comb, which
will avoid this problem.

On the other hand, there is a lot legacy Verilog code that doesn't use
always_comb. It doesn't have a problem with 2-state variables, since
those didn't exist in Verilog either. But it *does* have a problem if
the Verilog simulator used an execution order that made it work, but
SystemVerilog simulators are required to use an order that guarantees
that it won't work.

>Do you want the initial values of 2 state variables to also generate
>events?

We could discuss that, but it isn't necessary to making legacy Verilog
code work, since that code doesn't contain any 2-state variables.

Steven Sharp
sharp@cadence.com
Received on Thu Dec 9 19:21:56 2004