Re: [sv-bc] Errata: variable initializers don't match Verilog-2001

Another point of view on this might be that, while this is not compatible
with Verilog-2001, the benefits of greater determinacy are sufficient to
justify making the change. But in that case, wouldn't the same argument
apply to Verilog also? If this would be a good thing to change, then why
wouldn't it be better to change it in Verilog-2005?

Steven Sharp
sharp@cadence.com
Received on Sat Dec 4 15:27:02 2004