RE: [sv-bc] Errata: variable initializers don't match Verilog-2001

>From: Shalom.Bresticker@freescale.com
>
>Dave,
>
>> I believe the testbench section of SV depends on the currently defined
>> behavior,
>
>Can you be more specific?

Since Dave has not replied...

I asked the same thing at the SV-BC meeting. I pointed out that
testbenches get written in Verilog also, and asked what features
specific to SystemVerilog depend on this.

Dave mentioned program blocks. I said that I thought program blocks
executed in the reactive region, so variables would already have been
initialized before the program blocks execute, even with the 1364
rules. Dave expressed concern that initializers in program blocks
would also execute in the reactive region, preventing this. I said
that I didn't see any reason why initializers in program blocks
couldn't be defined to execute at the same time as initializers in
modules, and not in the reactive region. There was no further
discussion.

I think the real answer is that this was speculation on Dave's part.
It is possible that there is an issue here, but no evidence of it has
been presented.

Steven Sharp
sharp@cadence.com
Received on Thu Dec 9 12:46:26 2004