Re: [sv-bc] Errata: variable initializers don't match Verilog-2001

From: Steven Sharp <sharp@cadence.com>
Date: Thu Sep 02 2004 - 16:52:08 PDT

>A related question:
>
>When do supply0 and supply1 nets get their values?

In the simulators I have access to (XL and NC), they transition from
X to 0 or 1 at time 0 during simulation.

Steven Sharp
sharp@cadence.com
Received on Thu Sep 2 16:52:12 2004

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