Re: [sv-bc] Errata: variable initializers don't match Verilog-2001

>The latest example ... seems to imply that in order for the evaluation
>of a continuous assignment, an event on the RHS must be generated,
>including at time 0. However, a continuous assignment does not require
>an event on its RHS. For example:
>
> module init;
> wire w;
> assign w = 1;
> initial #1 $display( "wire is %b", w );
> endmodule
>
>The code above must also show '1' as the value of wire w, and no
>event is generated by the constant 1.

I believe that Verilog-XL gives special treatment to continuous
assignments where the RHS is a constant, and evaluates them specially.
For all others it relies on events to trigger them. So the fact
that this particular case works in a simulator does not necessarily
imply that all cases where there is no event generated will work in
that simulator.

However, it is possible to use a simulation algorithm that does not
rely on events at time zero to make continuous assignments work. I
don't consider this a strong argument for variable initialization
needing to match Verilog-2001.

The only argument that I have made is that this part of SystemVerilog
does not match Verilog-2001. Existing correct Verilog-2001 implementations
would have to modify their behavior on existing Verilog-2001 code in order
to match SystemVerilog.

Steven Sharp
sharp@cadence.com
Received on Fri Dec 3 19:22:31 2004