[sv-bc] Errata in SV 3.1a LRM Section 3.11: ambiguous about bit and part selects of packed unions

SV 3.1a, section 3.11, says with "a packed structure can be used as a whole
with arithmetic and logical operators", and that it is legal to do bit
selects and part selects of packed structures

For packed unions, the LRM says that "a packed union can be used as a whole
with arithmetic and logical operators", but makes no mention as to whether
bit and part selects are legal for packed unions. If bit/part selects of
packed unions are not allowed, why the limitation? If they are allowed,
then this should be mentioned in the LRM, as it is with packed structures.

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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062

Sutherland HDL, Inc. -- Training Engineers to be Verilog, SystemVerilog
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Received on Thu Sep 2 00:57:13 2004