Re: [sv-bc] Errata: variable initializers don't match Verilog-2001

From: <Shalom.Bresticker@freescale.com>
Date: Thu Sep 02 2004 - 01:39:17 PDT

A related question:

When do supply0 and supply1 nets get their values?

Shalom

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Received on Thu Sep 2 01:49:26 2004

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