RE: [sv-bc] Built-in types are not packed arrays

>V2K doesn't allow bit selects of its built-in integer types,
>'integer' and 'time'. (Yes, most simulators support it anyway.)
>So a V2K array of integers really does have just one dimension,
>not two.

This is incorrect. Verilog-1995 did not allow bit selects of the
integer types. Verilog-2001 does. See the change in the first
sentence in 4.2.1. So a V2K array of integers really does have
two dimensions, not one.

>Incidentally, I recommend against using the built-in integer
>types in synthesis, except for things like for-loop iteration
>variables, even though it will "work". As the V2K LRM says,
>"An integer is a general-purpose variable used for manipulating
>quantities that are not regarded as hardware registers."
>If you really want a 32-bit signed hardware register, declare
>its size explicitly.

Agreed. However, apparently enough people were using bit selects
of integers (which were allowed by XL) that they got officially
allowed in V2K.

Steven Sharp
sharp@cadence.com
Received on Fri Sep 24 12:37:54 2004