Re: [sv-bc] Built-in types are not packed arrays

>>Would you agree that $dimensions(byte) == 1?
>
>logic foo, bar;
>foo = bar[0];
>
>I'd even agree that $dimensions(logic) == infinity ;-)
>
>In Trenchard More's array theory this is called the "ungrounded"
>axiom system.

I don't know whether SystemVerilog changed this, but in Verilog it
is illegal to index into a scalar (though some tools may improperly
allow it anyway). That presumably "grounds" the system, and keeps
the number of indexes that can be applied finite.

Steven Sharp
sharp@cadence.com
Received on Fri Sep 24 14:52:36 2004