RE: [sv-bc] E-Mail Vote - Closes Midnight Oct 10

Adam,

If someone codes their state machine as:

always @(posedge clk) unique case (state)...

Then the unique case is synchronized to the clock.

In simulation, after time 0, run time errors and warnings have little difference; simulation continues. But during compilation and elaboration, an error will typically stop the process, whereas an warning just becomes noise.

I think users would like as soon as possible, that a unique or priority case has been coded wrong. The same holds for an assertion. If someone codes an assertion that elaborates to

assert property (0);

That should be an elaboration error, if the compiler is allowed to treat it that way.

Dave

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Adam Krolnik
Sent: Thursday, October 07, 2004 9:45 AM
To: Warmke, Doug
Cc: 'Brad.Pierce@synopsys.com'; sv-bc@eda.org
Subject: Re: [sv-bc] E-Mail Vote - Closes Midnight Oct 10

Hi Doug;

Requiring simulators to evaluate unique case branches and issue errors may cause false errors to be reported due to simulation evaluation artifacts and timed signal propagations.

We have shown in early sv-ac discussions that error checking synchronized to a clock is the safest way to avoid false failures.

Thus I think the change to warnings is prudent.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074
    Co-author "Assertion-Based Design"
Received on Thu Oct 7 10:40:34 2004