Re: [sv-bc] E-Mail Vote - Closes Midnight Oct 10

Hi Dave;

Yes, I agree with you for that case.

Have you consider this user's code:

// Delay from gates, other modules, system, etc.
assign #1 input3_with_delay = F(input4);

always @(input1 or input2 or input3_with_delay)
   begin
   unique case(1'b1)
     input1: ...
     input2: ...
     input3: ...

There can exist a case where more than one input (input1, input2, input3) is asserted,
for a simulation moment. This should not cause an error.

It can also be difficult to statically predict that a set of signals will obtain/not
obtain a specific combination of values. I can depend on equation complexity, input
patterns, reset states, etc.

I know the intent is to allow the user to say a set of case statements are mutually
exclusive. What role the simulator can have is difficult to express.
   Must it detect all cases?
   May it report warnings if it does detect a violation?
   Should it report errors if it detects a violation?

What roles should be allowed? Does the text allow for nothing, or errors, or warnings to
be reported? It seems the text is trying to require or allow for warnings/errors. Maybe
the text needs to use 'may' language, "a simulator may issue a ..."

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074
    Co-author "Assertion-Based Design"
Received on Thu Oct 7 10:58:09 2004