Re: [sv-ec] Re: [sv-bc] question on str.putc()

Below is my reasoning for the comments I made related to Shalom's question.

string x = "abc";
str[2] = "abc"; (1)
str[2] = x; (2)

str[2] is a character which in SV is a byte.
Statement (1) is a Verilog statement, so it must follow Verilog semantics.
Statement (2) should be illegal as an SV string variable cannot be assigned
directly to a byte, logic, etc.

Surrendra
At 05:29 PM 10/16/2004 -0400, you wrote:

> >> Why is this being defined inconsistently with other assignments in the
> >> language?
> >
> >I believe that the reason for this is due to the fact that the string
> >data type is based upon the C++ Standard Template Library implementation
> >of its string class. In the STL implementation the leftmost character
> >has index 0. This is consistent with how C-strings are used.
>
>I have no problem with specifying that the leftmost character has index 0,
>though the LRM fails to do so. Verilog allows specifying ranges in either,
>direction, so the predefined range for a string can easily be specified
>to have 0 for the leftmost character.
>
>The issue is with the truncation rules when assigning to that character.
>The comment in the example in 3.7 is wrong, and the note that Shalom
>pointed out is wrong if x is a string wider than 1 character.
>
>Steven Sharp
>sharp@cadence.com

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Surrendra A. Dudani
Synopsys, Inc.
377 Simarano Drive, Suite 300
Marlboro, MA 01752

Tel: 508-263-8072
Fax: 508-263-8123
email: Surrendra.Dudani@synopsys.com
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Received on Sun Oct 17 17:37:53 2004