Re: [sv-ec] Re: [sv-bc] question on str.putc()

3.7 has the example

reg [15:0] r ;
string a ;

r = a ; // OK

If you say that assignment does not appear in Table 3-2 (String operators),
I would say that assignment is not considered an operator.
3.6, for example, also separates assignments from operators.

If you refer to the sentence, "A string, string literal, or packed array
can be assigned to a string variable," that is referring to what can be
assigned to a string variable, not what a string can be assigned to.

Shalom

On Sun, 17 Oct 2004, Surrendra Dudani wrote:

> Below is my reasoning for the comments I made related to Shalom's question.
>
>
> string x = "abc";
> str[2] = "abc"; (1)
> str[2] = x; (2)
>
> str[2] is a character which in SV is a byte.
> Statement (1) is a Verilog statement, so it must follow Verilog semantics.
> Statement (2) should be illegal as an SV string variable cannot be assigned
> directly to a byte, logic, etc.

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Shalom Bresticker                        Shalom.Bresticker @freescale.com
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