Re: [sv-bc] E-mail Vote: Closes 12pm PST Nov 01

I vote YES on everything except 163, where I vote NO.

I don't believe it is desirable to have "reg" used interchangeably
with "logic" as a datatype. I think "reg" should be treated as
specifying a variable object kind, rather than a datatype. Even
if it is treated as a datatype, I don't believe it is desirable to
allow it to appear in all the places that "logic" can appear.
Experienced Verilog users will find it jarring, and perhaps confusing,
to allow declarations such as "parameter reg p = 0;" or
"function reg f;" or worst of all "wire reg w;"

Steven Sharp
sharp@cadence.com
Received on Wed Oct 27 17:34:45 2004