RE: [sv-bc] size of enums

I believe this is historical. In the orginal superlog donation all enums
where int (32 bit 2 state). In the System Verilog 3.0 (the fist SV LRM),
this was extended to allow size and type to be specified, but the default
was left int.

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Paul
> Graham
> Sent: Friday, October 29, 2004 11:35 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] size of enums
>
>
> SV defines that an enum's type defaults to int unless an explicit
> type declaration is given. So:
>
> typedef enum {false, true} boolean;
>
> is really a synonym for int. For synthesis this means that each
> boolean variable will generate 32 wires. The intent seems to be to
> force the user to explicitly size the enum type if he wants it to have
> minimal width. But this is troublesome:
>
> typedef enum logic [3:0] { red, orange, ..., mauve, pink, .... } colors;
>
> Adding new enum values will cause the type to overflow the bounds.
> Yet it's easy to set the bounds to be wider than necessary. The user
> has to count the enums, or play a game with the tool to find the minimum
> width that doesn't trigger an overflow error.
>
> Enums in vhdl are easier to use. If you declare;
>
> type colors is (red, orange, ...);
>
> then a synthesis tool can compute the minimum bitwidth by itself. This
> strikes me as being more maintainable and less error-prone than the SV
> approach.
>
> So what is the rationale for defaulting to type int for enums?
>
> Paul
Received on Fri Oct 29 12:44:17 2004