[sv-bc] DataTypes: Defining a data type in the LRM

I spent some time looking at the SystemVerilog "Data Types" chapter
to see what changes might be required to extend datatypes to nets.
It seems to me that we would need to be a little more precise about how
we talk about data types and data objects. For example, in section 3.1
there is a paragraph that talks about net data types and variable
data types as though they are different things. If we look at a data type
simply as a set of values, and we want to make those values available
to nets too, then we probably do not want to make this kind of distinction.

Here is a rough cut at defining a data type a little more formally
(in the 3.1 introductory section), plus an example of how we might want
to treat a data type as a set of values in other text (in section 3.6).

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SECTION 3.1:

CHANGE

Verilog-2001 has net data types, which can have 0, 1, X, or Z, plus 7
strengths, giving 120 values. It also has variable data types such as reg,
which have 4 values 0, 1, X, Z. These are not just different data types,
they are used differently. SystemVerilog adds another 4-value data type,
called logic (see Sections 3.3.2 and 5.5).

TO

Verilog-2001 has data objects that can take on values from a small number
of predefined value systems: the set of four-state logic values, vectors
and arrays of logic values, and the set of floating point values.
SystemVerilog extends Verilog by introducing some of the data types that
conventional programming languages provide, such as enumerations and
structures.

In extending the type system, SystemVerilog makes a distinction between
an object and its data type. A data type is a set of values and a set
of operations that can be performed on those sorts of values. Data types
can be used to declare data objects, or to define user-defined data types
that are constructed from other data types.

The Verilog-2001 logic system is based on a set of four state values:
0, 1, X, and Z. Although this four-state logic is fundamental to the
language, it does not have a name. SystemVerilog has given this primitive
data type a name, logic. This new name can be used to declare objects
and to construct other data types from the four-state data type.

CHANGE

Verilog-2001 provides arbitrary fixed length arithmetic using reg data
types. The reg type can have bits at X or Z, however, and so are less
efficient than an array of bits, because the operator evaluation must
check for X and Z, and twice as much data must be stored. SystemVerilog
adds a bit type which can only have bits with 0 or 1 values. See
Section 3.3.2 on 2-state data types.

TO

Verilog-2001 provides arbitrary fixed length arithmetic using 4-state
logic. The 4-state type can have bits at X or Z, however, and so may be
less efficient than an array of bits, because the operator evaluation must
check for X and Z, and twice as much data must be stored. SystemVerilog
a bit data type that can only have bits with 0 or 1 values.
See Section 3.3.2 on 2-state data types.

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Section 3.6

CHANGE

The chandle data type represents storage for pointers passed using
the DPI Direct Programming Interface (see Section 27). The size of this
type is platform dependent, but shall be at least large enough to hold
a pointer on the machine in which the tool is running.

TO

The chandle data type represents storage for pointers passed using
the DPI Direct Programming Interface (see Section 27). The size of
a value of this type is platform dependent, but shall be at least
^^^^^^^^^^
large enough to hold a pointer on the machine in which the tool
is running.

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Section 3.7

CHANGE

SystemVerilog includes a string data type, which is a variable size,
dynamically allocated array of bytes. SystemVerilog also includes
a number of special methods to work with strings.

TO

SystemVerilog includes a string data type. The values of the string
type are dynamically allocated arrays of bytes that can vary in size.
SystemVerilog also includes a number of special methods to work with strings.
Received on Wed Nov 3 14:28:58 2004