Re: [sv-bc] default initial value issues

Mark Hartoog wrote:

>>Issue 286 also interacts with issue 216, on initializing
>>4-state enums to X.
>>
>>
>
>There have been two views of what enums should be in System Verilog.
>
>....
>
>If we want to change the initialization of 4 state enums, then I would
>be strongly opposed to making the initialization of 4 state enums different
>then 2 state enums. All enums should initialize in the same way. This means
>either first label or the default initial value for the base type ('x' for
>4 state and '0' for 2 state).
>
I think we need to look at these kind of things in the context of
general language extension. I suggested elsewhere that it would be
useful to be able to extend enums e.g. if I want to define my own
4-state and 2-state logic:

    enum my_2_state {L,H};
    enum my_4_state extends my_2_state {X,Z}; // 4-states are L,H,X,Z

If I do something like that then it is useful to be able to change the
default for the 4-state to be X rather than L (if that's the default for
my_2_state). E.g.:

    enum my_4_state extends my_2_state {X,Z} = X; // make X the 4-state
default.
    enum my_5_state extends my_4_state {U} = U; // add an "unset"
state and make it the default.

    enum my_4_state_0 extends _sv_4_state = L; // Same as my_4_state but
default is L;

Note: if you use "extended" enums then the base enums are compatible: a
my_2_state could be used where my_5_state is required if strict typing
is being enforced.

Just a thought...
Kev.

>
>Mark Hartoog
>700 E. Middlefield Road
>Mountain View, CA 94043
>650 584-5404
>markh@synopsys.com
>
>
>

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