Personally, I think time units and timescales are amongst the worst
features in Verilog (much more troublesome in practice than defparams,
for example ...).
I'm sorry that SV took the route of extending them.
Shalom
-- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential ProprietaryReceived on Thu Nov 4 01:25:26 2004
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