Thanks, Brad.
If you want to see how the terms "error" and "warning" are used in 1364
and SV, you should search for the terms "error" and "warning" and not just
for "error message" and "warning message".
I think that different meanings for these terms might apply in the PLI
than in the HDL itself.
Looking through 1364, I think their use is not consistent.
But since SV is new, there should be an attempt to be consistent at least
from now. Certainly where the terms are used several times on the
same page.
Generally, one should be careful about specifying that some situation
will have a fatal effect, causing the simulation to end or turning
everything to X, etc. Only if there really is no alternative, no other
way to continue.
Users are a very imaginative bunch.
After 15 years using Verilog, I'm still seeing new uses occasionally.
Shalom
-- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential ProprietaryReceived on Thu Nov 4 00:57:21 2004
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