Re: [sv-bc] Errata in SV 3.1a LRM Section 18.4: inconsistent use of error and warning

>Adam says, however, in http://www.eda.org/sv-bc/hm/2047.html
>that --
>
> "Requiring simulators to evaluate unique case branches and
> issue errors may cause false errors to be reported due to
> simulation evaluation artifacts and timed signal propagations."
>
>Does this mean that it is actually legal to violate the
>uniqueness assertion, or just that a simulator could get confused
>about whether the assertion was violated?

I assume that he means that the simulator determines that the assertion
is violated (without being confused), but that the user may not care
about the violation except at certain times. For example, there might
be a zero-width glitch into an illegal state and then back to a legal one.
Say a one-hot encoding is changing state and it momentarily passes through
a state with two bits hot. This might depend on event ordering that is
considered nondeterministic.

I don't see how a simulator can do anything about this. All it can do
is test the condition when the case is evaluated, and report any violations.

> Adam continues --
>
> "We have shown in early sv-ac discussions that error checking
> synchronized to a clock is the safest way to avoid false failures.
>
> "Thus I think the change to warnings is prudent."

I would interpret this as an argument that violations should not be
treated as fatal to the simulation, since there may be violations that
the user wants to ignore.

Steven Sharp
sharp@cadence.com
Received on Thu Nov 4 18:12:24 2004