[sv-bc] DataTypes: the reg datatype

I feel that there is a big disconnect between the proposals from Cadence and SystemVerilog in that the 'unnamed 0,1,x,z data' type in the Cadence proposal is in deed what SystemVerilog called the 'reg datatype', and created a new name for that datatype, 'logic'. (Sometimes I get the funny feeling that we are debating Creationism versus Evolutionism)

If we define the datatype on wires feature as simply a casting and type equivalence mechanism, then can limit the amount of changes needed to the LRM.

Dave

David Rich
Verification Technologist
Design Verification & Test Division
Mentor Graphics Corporation
dave_rich@mentor.com
Office:   408 487-7206
Cell:     510 589-2625
Received on Thu Nov 4 07:45:55 2004