RE: [sv-bc] DataTypes: BNF changes

>There is already a lexical restriction in Verilog for things like a
>space between two ampersands:
>
>A & & B

BTW, I looked for this restriction in the 1364 LRM to see if there was
any useful wording, and did not find it. Apparently this is just a
de fact standard based on the fact that Verilog-XL produces an error
for it.

Steven Sharp
sharp@cadence.com
Received on Wed Nov 10 15:47:35 2004