Re: [sv-bc] DataTypes: BNF changes

I did not find it, either.

Although Verilog-XL produces an error, NC-Verilog only produces a warning, which
is nice,
and VCS doesn't say anything.

Shalom

Steven Sharp wrote:

> >There is already a lexical restriction in Verilog for things like a
> >space between two ampersands:
> >
> >A & & B
>
> BTW, I looked for this restriction in the 1364 LRM to see if there was
> any useful wording, and did not find it. Apparently this is just a
> de fact standard based on the fact that Verilog-XL produces an error
> for it.
>
> Steven Sharp
> sharp@cadence.com

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