[sv-bc] uwire data type and System Verilog

The BTF task force has voted to add single driver nets (uwire I
believe is the current name) to the Verilog 2005 LRM. These are
similar to stdulogic in VHDL. It should be a compile time error
if a uwire net has more than one driver.

I think that this addition to Verilog 2005 requires some additions
to the System Verilog LRM. Here is some of the text from the Verilog
2005 proposal (perhaps not the final text):

> A wone net is very similar to a wire net. It differs in the following two
> ways:
>
> 1) It is an error for a wone net to have more than one driver
>
> 2) An implementation must either collapse a port connection
> to a wone net, or it must warn that it is not collapsing.
>
> When collapsing a wone port connection, the net type of the simulated net
> is resolved as follows:
>
> NET TYPE 1 NET TYPE 2 RESOLUTION WARNING
> wone wone wone No
> wone wire/tri wone No
> wone wand/triand wone Yes
> wone wor/trior wone Yes
> wone trireg wone Yes
> wone tri0 wone Yes
> wone tri1 wone Yes
> wone supply0 supply0 No
> wone supply1 supply1 No
>
> When the net type coercion results in a different behavior (such as when
> a trireg and a wone are connected, resulting in a wone), a warning must
> be issued.

Because variable input/output ports are allowed, the situation is more
complex in System Verilog. Consider this case:

module top();
wire w;
mid u1(w);
mid u2(w);
endmodule

module mid(output logic o);
bot u1(o);
endmodule

module bot(output uwire o);
endmodule

If the bot port is a wire rather than uwire, this is a perfectly
legal System Verilog design. With the uwire port on bot, is this
a legal design? Should it give any non-fatal error messages or
warnings?

Mark Hartoog
700 E. Middlefield Road
Mountain View, CA 94043
650 584-5404
markh@synopsys.com

Mark Hartoog
700 E. Middlefield Road
Mountain View, CA 94043
650 584-5404
markh@synopsys.com
Received on Wed Nov 10 16:27:24 2004