RE: [sv-bc] Deadline for detailed feedback on Data Types on Nets Proposal

> > typedef struct { reg a; } ST;
> > var ST sv;
> > wire ST sw;
> >
> > Now sv.a is a variable with data type reg and sw.a is a net with a
> > resoultion function of a wire and a data type of reg.
>
> With the semantics I prefer, I would say with the first case you've
> created a net sv.a with a driver of type logic.

I don't understand how 'sv.a' could be considered a 'net'. With the 'var'
keyword in front of the 'sv' variable declaration I think this is clearly
a variable.

> sw I would consider illegal (as below).

We could make it illegal to use 'reg' in a struct, but that would create
backwards compatibility problems with lots of existing System Verilog code.
We could also make 'reg' illegal in a struct that was used on a net
declaration. That would not have backwards compatibility issues, because
data types have never been allowed on nets before.

> I'm just saying I don't think "reg" in a struct with its old Verilog
> meaning needs to be illegal.
>
> Personnally, I'd like to be able to do something like:
>
> typedef struct { reg a;
> int metadata; } ST;
>
> function drive_st(var ref rst,logic d,int meta)
> rst = {d,meta};
> endfunction
>
> module foo (...,output o,...);
>
> var ST sv;
>
> alias sv.a = o; // bind sv.a to output wire o
>
> always @(clk1) drive_st(sv,1,1);
>
> always @(clk2) drive_st(sv,0,2);
>
> ...
>
> endmodule
>
> - i.e. I can group net and variable data in a struct.
>
> I'd really like to do it with classes too, so that I could make the drive
> function a class member - but I'll leave that one for later :-)

I'm not 100% sure what you are trying to do in this example. Are you trying
to create a struct where some fields are variables and some fields are nets?

You can do that with an interface, but interfaces can only be used as ports.
The current data types on wires proposal does not include a way of
making some fields of a struct a net and other fields a variable.

The alias statement in your example is illegal I believe. You can only
alias nets. I think you are trying to convert a variable to a net with
this alias statement, but this is not currently allowed in System Verilog.

I do not think there is time at this point to consider structs with a mixture
of net and variable fields for this version of the LRM.

> -----Original Message-----
> From: Kevin Cameron [mailto:kcameron@altera.com]
> Sent: Monday, November 15, 2004 3:46 PM
> To: Mark Hartoog
> Cc: Brad.Pierce@synopsys.COM; sv-bc@eda.org; sv-ec@eda.org
> Subject: RE: [sv-bc] Deadline for detailed feedback on Data Types on
> Nets Proposal
>
>
>
>
> On Mon, 15 Nov 2004, Mark Hartoog wrote:
>
> > > If you view a struct as just a collection of objects then I would
> > > expect the object s.a to behave the same as (say) "reg s_a",
> > > so why would it be illegal?
> > >
> > > If you consider reg as a declaration of a driver & signal/signal-reference
> > > (which I do) then I think you would have disallow associating a struct
> > > with a net if it contains reg types, but I don't see a reason for not
> > > allowing references to it or other variable usage.
> >
> > The struct is a data type that can be used to declare both nets and variables.
> > Using the 'var' keyword for variables and saying 'reg' is a data type we have:
> >
> > typedef struct { reg a; } ST;
> > var ST sv;
> > wire ST sw;
> >
> > Now sv.a is a variable with data type reg and sw.a is a net with a
> > resoultion function of a wire and a data type of reg.
>
> With the semantics I prefer, I would say with the first case you've
> created a net sv.a with a driver of type logic.
>
> sw I would consider illegal (as below).
>
> > On the other hand if we say that the 'reg' keyword is for variables,
> > then:
> >
> > typedef struct { reg a; } ST;
> > reg ST sv;
> > wire ST sw;
> >
> > This makes sv.a a variable of type 'logic' (default type for variables) and
> > sw.a a net with a resoultion function of a wire and a data type of 'logic'!!!
> > This seems wrong to me.
>
> With my preferred semantics I would consider those illegal since you would
> be nesting a net declaration inside another net declaration (which at best
> is going to be sematically messy).
>
> > The fields of a struct are not variables unless the struct type is used in
> > a variable declaration.
>
> Agreed.
>
> I'm just saying I don't think "reg" in a struct with its old Verilog
> meaning needs to be illegal.
>
> Personnally, I'd like to be able to do something like:
>
> typedef struct { reg a;
> int metadata; } ST;
>
> function drive_st(var ref rst,logic d,int meta)
> rst = {d,meta};
> endfunction
>
> module foo (...,output o,...);
>
> var ST sv;
>
> alias sv.a = o; // bind sv.a to output wire o
>
> always @(clk1) drive_st(sv,1,1);
>
> always @(clk2) drive_st(sv,0,2);
>
> ...
>
> endmodule
>
> - i.e. I can group net and variable data in a struct.
>
> I'd really like to do it with classes too, so that I could make the drive
> function a class member - but I'll leave that one for later :-)
>
> Kev.
>
> >
> > -----Original Message-----
> > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Kevin Cameron
> > Sent: Monday, November 15, 2004 2:35 PM
> > To: Mark Hartoog
> > Cc: Brad.Pierce@synopsys.COM; sv-bc@eda.org; sv-ec@eda.org
> > Subject: Re: [sv-bc] Deadline for detailed feedback on Data Types on Nets Proposal
> >
> >
> > Mark Hartoog wrote:
> >
> > I tend to agree that 'reg' should not be a data type and that it
> > would be better to use 'reg' instead of 'var'.
> >
> > Could someone please remind us again of the arguments for keeping
> > 'reg' as a data type that is equivalent to 'logic'?
> >
> >
> > I think it was sloppy usage in SuperLog that got grandfathered into SV.
> >
> > I'm not sure what the history of arguments on this are, but this
> > declaration, which is now legal would become illegal:
> >
> > typedef struct { reg a; } ST;
> > ST s;
> >
> > Since the fields of a struct are not variables but only data types.
> >
> > I would have thought the struct is a data-type and if it is used as a variable then
> the individual
> > fields would also be variables?
> >
> > If you view a struct as just a collection of objects then I would expect the object s.a
> to behave
> > the same as (say) "reg s_a", so why would it be illegal?
> >
> > If you consider reg as a declaration of a driver & signal/signal-reference (which I do) then I
> > think you would have disallow associating a struct with a net if it contains reg types, but I
> > don't see a reason for not allowing references to it or other variable usage.
> >
> > Kev.
> >
> > --
> > Altera Corp, 101 Innovation Drv, San Jose, CA 95134. T# (408) 544 7126
> >
> >
Received on Mon Nov 15 16:18:07 2004