[sv-bc] The "var" keyword

I would like to suggest the following approach to the var/reg/logic issue:

In 1364 Verilog, "reg" serves a dual purpose: it implies *both*
variable and four state. In trying to make it one or the other
in SystemVerilog, we are bound to confuse some people (depending
on whether you think that the "variable-ness" or the "four-state-ness"
is more significant).

SystemVerilog chose to make "reg" a data type. Perhaps we should not
put any more effort into redefining reg, and accept what the 3.1a LRM
says. We could instead focus our efforts on providing an additional
-- and less ambiguous -- alternative moving forward.

The 1364 Verilog LRM transitioned from the term "register" to "variable".
We could introduce a keyword that matches the LRM terminology and does not
have baggage associated with it: "var". Moving forward in IEEE SystemVerilog,
"reg" would still be valid as a data type; however, the keywords of choice
would be "logic" for four-state and "var" for variable.
Received on Mon Nov 15 16:30:05 2004