Re: [sv-bc] The "var" keyword

> From - Mon Nov 15 18:27:54 PST 2004
>
> I would like to suggest the following approach to the var/reg/logic issue:
>
> In 1364 Verilog, "reg" serves a dual purpose: it implies *both*
> variable and four state. In trying to make it one or the other
> in SystemVerilog, we are bound to confuse some people (depending
> on whether you think that the "variable-ness" or the "four-state-ness"
> is more significant).

"reg" doesn't do what you say. In Verilog a reg declaration creates a
behavioral driver for a net, if the net is not connected out of the
module then it looks like a variable. The type of the driver is 4-state
- which is the data-type "logic" in SV - the net can support the extend
range of signal strengths so is not actually restricted to 4-state.
 
> SystemVerilog chose to make "reg" a data type. Perhaps we should not
> put any more effort into redefining reg, and accept what the 3.1a LRM
> says. We could instead focus our efforts on providing an additional
> -- and less ambiguous -- alternative moving forward.

Someone decided that since "reg foo" appeared to declare a variable they
would just use "reg" as a synonym for "logic", however that causes problems
when you need to differentiate between something that is a driver and something
that is just a variable.

I'm not suggesting anything be redefined wrt Verilog, just that reg should
perform the same task in SV and not be used as a synonym for "var logic".

Kev.

> The 1364 Verilog LRM transitioned from the term "register" to "variable".
> We could introduce a keyword that matches the LRM terminology and does not
> have baggage associated with it: "var". Moving forward in IEEE SystemVerilog,
> "reg" would still be valid as a data type; however, the keywords of choice
> would be "logic" for four-state and "var" for variable.
Received on Tue Nov 16 00:25:57 2004