RE: [sv-bc] The "var" keyword

In what way does it not work like that?

One of the main reasons I'm involved in this committee is to try and
make sure that SV does not become incompatible with Verilog-AMS, and to
do that there needs to be a clear understanding of what constitutes a
driver and what its type is vs the type of the net. The reg statement in
Verilog (and hence Verilog-AMS) defines a digital driver.

If SV loses the explicit declaration of drivers and goes for some fuzzy
approach then it becomes very difficult to make AMS work properly (back
annotation of timing also becomes awkward).

Kev.

-----Original Message-----
Shalom.Bresticker@freescale.com
 
Kevin,

> "reg" doesn't do what you say. In Verilog a reg declaration creates a
> behavioral driver for a net, if the net is not connected out of the
> module then it looks like a variable. The type of the driver is
4-state
> - which is the data-type "logic" in SV - the net can support the
extend
> range of signal strengths so is not actually restricted to 4-state.

This may be the way you would like to look at it, but that is not what
the IEEE Std 1364 Verilog LRM says. You will not find there any
statement
supporting that interpretation. Nor do implementations work that way.

Now it may be that different interpretations are equivalent in current
Verilog. But certainly, Kathy's is closer to the language of the LRM
and therefore simpler and more straightforward. So you can't claim that
your interpretation is right and hers is wrong.

Regards,
Shalom

-- 
Shalom Bresticker                        Shalom.Bresticker
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