We have distributed the data types on wires internally for review.
Some people who are not familiar with this proposal have been confused
by the language in the proposal.
The specific issue is the difference between "wire" and "wire logic".
Some people have interpreted the LRM language to mean the "wire" is
a net that has the Verilog net value system with 120 values, while
"wire logic" is a new kind of net that only has 4 values.
I don't think this was the intention at all, but some of the LRM changes
can apparently be read to mean this. In particular the change to the
3.1 introductory section and the diagram in the introduction.
The 3.1 introductory section removed language that talked about the
Verilog net data type having 0, 1, x, z, and 7 drive strengths giving
a total of 120 values, and replaces it with language that only talks
about 4 state values. Although later on in section 5.5 on Nets is says
"There is no change to the Verilog-2001 semantics related to net resolution
at the bit level, the role of strength, or the treatment of the signed
property across hierarchical boundaries.", the removal of the language
talking about net strength and the 120 values from I think 3.1 misled
readers.
I think it would be better if the 3.1 introduction makes clear that variables
have only a data type and are therefore 4 value, while nets with data types
have the 4 values, plus strength and net type which specify 120 values
and the resolution functions for multiple drivers. It would also be a good
idea to add strength to the diagram to make clear that nets also have
strength, but variables do not.
Mark Hartoog
700 E. Middlefield Road
Mountain View, CA 94043
650 584-5404
markh@synopsys.com
Received on Wed Nov 17 12:11:52 2004
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