RE: [sv-bc] Deadline for detailed feedback on Data Types on Nets Proposal

Hi Mark,

We proposed to remove that paragraph on net strength from the 3.1
introductory section because strength is not actually part of
the value of a net. Here are the IEEE Std 1364 sections that
describe value and strength:

    3.1 Value set

    The Verilog HDL value set consists of four basic values:

    0 - represents a logic zero, or a false condition
    1 - represents a logic one, or a true condition
    x - represents an unknown logic value
    z - represents a high-impedance state

    The values 0 and 1 are logical complements of one another.

    When the z value is present at the input of a gate, or when it is
    encountered in an expression, the effect is usually the same as an
    x value. Notable exceptions are the metal-oxide semiconductor (MOS)
    primitives, which can pass the z value.

    Almost all of the data types in the Verilog HDL store all four basic
    values. The exception is the event type (see 9.7.3), which has no
    storage. All bits of vectors can be independently set to one of
    the four basic values.

    The language includes strength information in addition to the basic
    value information for net variables. This is described in detail in 7.

    7.10 Strengths and values of combined signals

    In addition to a signal value, a net shall have either a single
    unambiguous strength level or an ambiguous strength consisting of
    more than one level. When signals combine, their strengths and values
    shall determine the strength and value of the resulting signal in
    accordance with the principles in 7.10.1 through 7.10.4.

The rest of 7.10 continues to discuss strength as separate information;
I will not include it all here.

Kathy

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>From: "Mark Hartoog" <Mark.Hartoog@synopsys.com>
>To: "Maidment, Matthew R" <matthew.r.maidment@intel.com>, <sv-bc@eda.org>,
> <sv-cc@eda.org>, <sv-ec@eda.org>
>Subject: RE: [sv-bc] Deadline for detailed feedback on Data Types on Nets Proposal
>Date: Wed, 17 Nov 2004 12:12:52 -0800
>
>We have distributed the data types on wires internally for review.
>Some people who are not familiar with this proposal have been confused
>by the language in the proposal.
>
>The specific issue is the difference between "wire" and "wire logic".
>Some people have interpreted the LRM language to mean the "wire" is
>a net that has the Verilog net value system with 120 values, while
>"wire logic" is a new kind of net that only has 4 values.
>
>I don't think this was the intention at all, but some of the LRM changes
>can apparently be read to mean this. In particular the change to the
>3.1 introductory section and the diagram in the introduction.
>
>The 3.1 introductory section removed language that talked about the
>Verilog net data type having 0, 1, x, z, and 7 drive strengths giving
>a total of 120 values, and replaces it with language that only talks
>about 4 state values. Although later on in section 5.5 on Nets is says
>"There is no change to the Verilog-2001 semantics related to net resolution
>at the bit level, the role of strength, or the treatment of the signed
>property across hierarchical boundaries.", the removal of the language
>talking about net strength and the 120 values from I think 3.1 misled
>readers.
>
>I think it would be better if the 3.1 introduction makes clear that variables
>have only a data type and are therefore 4 value, while nets with data types
>have the 4 values, plus strength and net type which specify 120 values
>and the resolution functions for multiple drivers. It would also be a good
>idea to add strength to the diagram to make clear that nets also have
>strength, but variables do not.
>
>Mark Hartoog
>700 E. Middlefield Road
>Mountain View, CA 94043
>650 584-5404
>markh@synopsys.com
Received on Wed Nov 17 12:49:38 2004