RE: [sv-bc] SV-BC #110 - 2-State Divide by 0 question

Cliff,

I suggest adding to SV section 7.4, which covers the rules for bit and logic
operations.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
+1-503-692-0898
  

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Clifford E. Cummings
> Sent: Tuesday, November 23, 2004 4:06 PM
> To: sv-bc@eda.org
> Subject: [sv-bc] SV-BC #110 - 2-State Divide by 0 question
>
> Hi, All -
>
> Don Mills and I have been asked to make a proposal for Issue
> #110 on divide by 0 in 2-state.
>
> I believe Don and I will propose that divide by 0 in 2-state
> just gives zero as a result. The problem is that the errata
> refers to a 1364 section and I am not sure where we should
> add this in the SystemVerilog standard.
> There is no addition-operator related section in the SV
> standard to amend with this information.
>
> Any suggestions?
>
> Regards - Cliff
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com Expert
> Verilog, SystemVerilog, Synthesis and Verification Training
>
>
>
>
Received on Tue Nov 23 16:22:21 2004