RE: [sv-bc] SV-BC #110 - 2-State Divide by 0 question

Hi, All -

I cannot be on the conference call on Tuesday, but here is my proposal.
Feel free to modify to taste. Thanks to all contributing feedbackers (is
this really a word?? :-)

Per Stu's recommendation, add another paragraph to section 7.4. Add the new
paragraph after the existing 2nd paragraph of section 7.4.

=====

(Existing 2nd paragraph - leave as is)
The operators != and == return an X if either operand contains an X or a Z,
as in Verilog-2001. This is converted to a 0 if the result is converted to
type bit, e.g. in an if statement.

PROPOSAL: (ADD after 2nd paragraph)
An arithmetic operation that returns either an X or a Z, as in
Verilog-2001, shall be converted to a 0 if the result is converted to a
2-state type.

(Cliff proposes ... )

=====

Review-Notes:

Matt's comments are addressed by this proposal. I agree that passing types
to a module that does legal divide-by-0 using 4-state types should not fail
or unnecessarily warn when a 2-state type is passed to the module.

Dave & Steve's comments are the driving idea behind the proposal.

Doug Warmke's comments were considered and even though this is not his
preferred resolution, I think it is a reasonable implementation and I think
Doug is okay with this idea.

Assertions - Matt notes that assertions can be added (I like it), and Doug
notes that one does not want to add assertions to all division operations
(also probably true). If the engineer is concerned about divide-by-0, the
engineer may want to create and exclusively use a user-defined division
function with divide-by-0 checking assertion added to the function.

Cliff-note - at some point in the future, we may want to implement
reproducible random initialization, per the paper that Lionel Bening and I
did at Boston SNUG and at that time, both paragraphs may change from
assigning 0 to assigning the appropriate reproducible random 2-state value.
This is a future enhancement and something that should be addressed by the
future 2-state datatypes proposal.

www.sunburst-design.com/papers/CummingsSNUG2004Boston_2StateSims.pdf

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training
Received on Mon Nov 29 10:26:11 2004