Re: [sv-bc] Proposal for compatibility problems with mixed Verilog/SystemVerilog code

File extension rules would require you to rename every one of your files.

Shalom

Mark Hartoog wrote:

> I am not thrilled with this proposal. This is trying to solve a real
> problem, but this is the most awkward way of solving this problem
> for users.
>
> If you have -v and -y libraries, you will need to put the `keywords
> on every single library file, since you have no control over what
> order these files are read. If you are using a mix of P1800 and
> 1364-2001 tools, you will have to have two versions of all your
> libraries, one with the `keywords for P1800 tools and one without
> the keywords for 1364-2001 tools. You might be able to avoid
> duplicating all the source using a P1800 library like:
>
> `keywords "1364-2001"
> `include <actual 1364 souce file>
> `endkeywords
>
> But you still end up with two complete libraries.
>
> Using file extension rules to distinguish keyword sets requires
> no changes to the users actual source code and will allow the
> same libraries to work with P1800 and 1364-2001 tools.
> Unfortunately, file extension rules are really outside the
> domain of the current LRM.
>
> Mark Hartoog
> 700 E. Middlefield Road
> Mountain View, CA 94043
> 650 584-5404
> markh@synopsys.com

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Shalom Bresticker                        Shalom.Bresticker @freescale.com
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