RE: [sv-bc] Proposal for compatibility problems with mixed Verilog/SystemVerilog code

Here's a paraphrased old suggestion for reducing the number of clashing
keywords:

A possible solution to the type name problem is to add some extra

functionality to SV, namely:

    untypedef <name>

If the existing (clashing) types (e.g. logic) are reimplemented as
predefined typedefs then they can be undefined when old code is
encountered e.g.:

    typedef _sv_type_logic logic; // pre-defined at start-up

    untypedef logic; // forget "logic"

    `include "old_code.v"

    untypedef logic; // in case it got typedef'd again

    typedef _sv_type_logic logic; // reinstate old definition

This should be relatively easy to implement since the type scheme in SV
is handled dynamically and this change wouldn't break any existing SV
code. You could temporarily limit the functionality to only allow the
redefinition to be the same as the first definition (which makes it even
easier to implement), but I think in the long term a mechanism is
required that allows local redefinition of types anyway.

Kev.

 
Received on Tue Nov 30 10:11:52 2004